Stardate 20011119.1404 (On Screen): When the original concept for Reduced Instruction Set Computing (RISC) was originally proposed, the idea was that you would implement a relatively small set of instructions. That would mean the instructions would be smaller and thus could be retrieved faster from memory, but also meant that the CPU would be simpler and thus could run at a higher clock rate. So you would partake something of the virtues of microcode; you'd use a lot of instructions instead of a few, but you'd still execute faster.
All well and good. So why is it that all the major RISC designs are still struggling to reach 1 GHz, a clock rate that AMD and Intel left in the dust more than a year ago with their ultra-complex instruction set x86's? Intel is shipping a 2 GHz P4, and AMD has produced a 1.6 GHz Palomino and will probably hit 2 GHz with the Thoroughbred sometime early next year. I'm aware that clock rate is not everything, God knows, but it still seems strange to me that all of the major RISC designs (ARM, Itanium, PPC, SPARC) are still stuck under 1 GHz. Wasn't the whole point of RISC that the simpler design would permit higher clock rates? (discussion in progress)
Some points about this. First, ARM hasn't actually been trying to be fast; their market doesn't need it. What's important for ARM is that it be small, cheap, and low power. Second, there hasn't been an honest RISC or CISC chip for at least ten years. The P4 and the Athlon are both implemented with internal microcode engines, and the ostensible big RISC chips like PPC and Itanium have long since abandoned the original principles of the Reduced Instruction Set. Originally, for instance, there wasn't even going to be a divide, let along floating point or SIMD.
