142 lines
8.3 KiB
C
142 lines
8.3 KiB
C
/*
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* This file is part of the COMROGUE Operating System for Raspberry Pi
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*
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* Copyright (c) 2013, Eric J. Bowersox / Erbosoft Enterprises
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* All rights reserved.
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*
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* This program is free for commercial and non-commercial use as long as the following conditions are
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* adhered to.
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*
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* Copyright in this file remains Eric J. Bowersox and/or Erbosoft, and as such any copyright notices
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* in the code are not to be removed.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this list of conditions and
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* the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* "Raspberry Pi" is a trademark of the Raspberry Pi Foundation.
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*/
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#ifndef __X__16550_H_INCLUDED
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#define __X__16550_H_INCLUDED
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#ifdef __COMROGUE_INTERNALS__
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/*------------------------------------------------------------------------------------------------------------
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* Standard bits used in the registers of a 16550 UART. Note that not all of these bits are supported by the
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* BCM2835 mini-UART; they are included here for completeness.
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*------------------------------------------------------------------------------------------------------------
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*/
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/* Interrupt Enable Register (read/write) */
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#define U16550_IER_RXREADY 0x01 /* Receive Ready interrupt */
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#define U16550_IER_TXEMPTY 0x02 /* Transmit Empty interrupt */
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#define U16550_IER_ERRBRK 0x04 /* Error/Break iterrupt */
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#define U16550_IER_SINPUT 0x08 /* Status change interrupt */
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/* Interrupt Identification Register (read-only) */
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#define U16550_IIR_NOPENDING 0x01 /* Set if no interrupt is pending */
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#define U16550_IIR_ID_MASK 0x0E /* Pending interrupt mask */
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#define U16550_IIR_ID_ERRBRK 0x06 /* Error/Break interrupt */
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#define U16550_IIR_ID_RXREADY 0x04 /* Receive Ready interrupt */
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#define U16550_IIR_ID_RXTIMEOUT 0x0C /* Receive Timeout interrupt */
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#define U16550_IIR_ID_TXEMPTY 0x02 /* Transmit Empty interrupt */
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#define U16550_IIR_ID_SINPUT 0x00 /* Status change interrupt */
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#define U16550_IIR_RXFIFO 0x40 /* Receive FIFO enabled */
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#define U16550_IIR_TXFIFO 0x80 /* Transmit FIFO enabled */
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/* FIFO Control Register (write-only) */
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#define U16550_FCR_ENABLE 0x01 /* Enable FIFOs */
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#define U16550_FCR_RXCLEAR 0x02 /* Clear receive FIFO */
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#define U16550_FCR_TXCLEAR 0x04 /* Clear transmit FIFO */
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#define U16550_FCR_MODE 0x08 /* FIFO mode select */
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#define U16550_FCR_LEVEL_MASK 0xC0 /* FIFO level mask */
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#define U16550_FCR_LEVEL_1 0x00 /* FIFO level: 1 character */
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#define U16550_FCR_LEVEL_4 0x40 /* FIFO level: 4 characters */
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#define U16550_FCR_LEVEL_8 0x80 /* FIFO level: 8 characters */
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#define U16550_FCR_LEVEL_14 0xC0 /* FIFO level: 14 characters */
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/* Line Control Register (read/write) */
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#define U16550_LCR_LENGTH_MASK 0x03 /* Data length control mask */
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#define U16550_LCR_LENGTH_5 0x00 /* Data length: 5 bits */
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#define U16550_LCR_LENGTH_6 0x01 /* Data length: 6 bits */
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#define U16550_LCR_LENGTH_7 0x02 /* Data length: 7 bits */
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#define U16550_LCR_LENGTH_8 0x03 /* Data length: 8 bits */
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#define U16550_LCR_STOP 0x04 /* Set = 2 stop bits, Clear = 1 stop bit */
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#define U16550_LCR_PARITY_MASK 0x38 /* Parity control mask */
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#define U16550_LCR_PARITY_NONE 0x00 /* Parity: NONE */
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#define U16550_LCR_PARITY_ODD 0x08 /* Parity: ODD */
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#define U16550_LCR_PARITY_EVEN 0x18 /* Parity: EVEN */
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#define U16550_LCR_PARITY_MARK 0x28 /* Parity: MARK */
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#define U16550_LCR_PARITY_SPACE 0x38 /* Parity: SPACE */
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#define U16550_LCR_BREAK 0x40 /* Send BREAK when set */
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#define U16550_LCR_DLAB 0x80 /* Divisor Latch Access Bit */
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/* Modem Control Register (read/write) */
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#define U16550_MCR_DTR 0x01 /* Set Data Terminal Ready */
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#define U16550_MCR_RTS 0x02 /* Set Request To Send */
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#define U16550_MCR_OP1 0x04 /* Set General-Purpose Output 1 */
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#define U16550_MCR_OP2 0x08 /* Set General-Purpose Output 2 */
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#define U16550_MCR_LOOPBACK 0x10 /* Loopback test mode */
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/* Line Status Register (read-only) */
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#define U16550_LSR_RXDATA 0x01 /* Received data ready */
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#define U16550_LSR_OVERRUNERR 0x02 /* Receiver overrun error */
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#define U16550_LSR_PARITYERR 0x04 /* Parity error */
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#define U16550_LSR_FRAMEERR 0x08 /* Framing error */
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#define U16550_LSR_BREAK 0x10 /* BREAK detected */
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#define U16550_LSR_TXBUFEMPTY 0x20 /* Transmitter buffer empty */
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#define U16550_LSR_TXEMPTY 0x40 /* Transmitter empty */
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/* Modem Status Register (read-only) */
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#define U16550_MSR_DELTA_CTS 0x01 /* change in Clear To Send line */
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#define U16550_MSR_DELTA_DSR 0x02 /* change in Data Set Ready line */
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#define U16550_MSR_DELTA_RI 0x04 /* change in Ring Indicator line */
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#define U16550_MSR_DELTA_CD 0x08 /* change in Carrier Detect line */
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#define U16550_MSR_CTS 0x10 /* Clear To Send */
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#define U16550_MSR_DSR 0x20 /* Data Set Ready */
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#define U16550_MSR_RI 0x40 /* Ring Indicator */
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#define U16550_MSR_CD 0x80 /* Carrier Detect */
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/* BCM2835-specific: Auxiliary control register (read/write) */
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#define AUXMU_CNTL_RXENABLE 0x00000001 /* Receiver enable */
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#define AUXMU_CNTL_TXENABLE 0x00000002 /* Transmitter enable */
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#define AUXMU_CNTL_RXAUTOFLOW 0x00000004 /* Reciever auto-flow-control enabled */
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#define AUXMU_CNTL_TXAUTOFLOW 0x00000008 /* Transmitter auto-flow-control enabled */
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#define AUXMU_CNTL_RXAUTO_MASK 0x00000030 /* Receiver auto-flow-control level */
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#define AUXMU_CNTL_RXAUTO_3 0x00000000 /* Receiver auto-flow-control: 3 spaces remaining */
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#define AUXMU_CNTL_RXAUTO_2 0x00000010 /* Receiver auto-flow-control: 2 spaces remaining */
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#define AUXMU_CNTL_RXAUTO_1 0x00000020 /* Receiver auto-flow-control: 1 space remaining */
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#define AUXMU_CNTL_RXAUTO_4 0x00000030 /* Receiver auto-flow-control: 4 spaces remaining */
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#define AUXMU_CNTL_RTSASSERT 0x00000040 /* RTS assert level invert */
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#define AUXMU_CNTL_CTSASSERT 0x00000080 /* CTS assert level invert */
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/* BCM2835-specific: Auxiliary status register (read-only) */
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#define AUXMU_STAT_RXREADY 0x00000001 /* Receive ready */
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#define AUXMU_STAT_TXREADY 0x00000002 /* Transmit ready */
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#define AUXMU_STAT_RXIDLE 0x00000004 /* Receiver idle */
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#define AUXMU_STAT_TXIDLE 0x00000008 /* Transmitter idle */
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#define AUXMU_STAT_RXOVERRUN 0x00000010 /* Receiver overrun */
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#define AUXMU_STAT_TXFULL 0x00000020 /* Transmit FIFO is full */
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#define AUXMU_STAT_RTS 0x00000040 /* Request To Send line */
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#define AUXMU_STAT_CTS 0x00000080 /* Clear To Send line */
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#define AUXMU_STAT_TXDONE 0x00000100 /* Transmitter done (Tx idle, FIFO empty) */
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#define AUXMU_STAT_RXLEVEL_MASK 0x000F0000 /* Receive FIFO fill level mask */
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#define AUXMU_STAT_TXLEVEL_MASK 0x0F000000 /* Transmit FIFO fill level mask */
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#endif /* __COMROGUE_INTERNALS__ */
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#endif /* __X__16550_H_INCLUDED */
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