split the low-level memory manager functions into their own assembly source
file down in the mm subdirectory
This commit is contained in:
Eric J. Bowersox
parent
61ff5d8db4
commit
e316553b81
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@ -30,7 +30,6 @@
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* "Raspberry Pi" is a trademark of the Raspberry Pi Foundation.
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*/
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#include <comrogue/internals/asm-macros.h>
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#include <comrogue/internals/mmu.h>
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.section ".text"
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@ -97,154 +96,3 @@ llIODelay:
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pop {lr}
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.delayreturn:
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bx lr
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/*
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* Flushes the system cache of all data on a page. Optionally writes back writeable data before flushing.
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*
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* Parameters:
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* - vmaPage = The page to be invalidated.
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* - bWriteback = TRUE to write back before invalidating, FALSE to not do so.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushCacheForPage
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_MmFlushCacheForPage:
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mov r2, # SYS_PAGE_SIZE
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sub r2, r2, #1
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orr ip, r0, r2 /* expand so that [r0, ip] is the range to invalidate */
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bic r0, r0, r2
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tst r1, r1 /* is this a writeable page? */
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mcrrne p15, 0, ip, r0, c14 /* yes, clean and invalidate */
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mcrreq p15, 0, ip, r0, c6 /* no, just invalidate */
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mcrr p15, 0, ip, r0, c5 /* either way, invalidate instruction cache */
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bx lr
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/*
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* Flushes the system cache of all data in a section. Optionally writes back writeable data before flushing.
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*
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* Parameters:
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* - vmaSection = The section to be invalidated.
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* - bWriteback = TRUE to write back before invalidating, FALSE to not do so.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushCacheForSection
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_MmFlushCacheForSection:
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mov r2, # SYS_SEC_SIZE
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sub r2, r2, #1
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bic r0, r0, r2 /* expand so that [r0, ip] is the range to invalidate */
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orr ip, r0, r2
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tst r1, r1 /* is this a writeable section? */
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mcrrne p15, 0, ip, r0, c14 /* yes, clean and invalidate */
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mcrreq p15, 0, ip, r0, c6 /* no, just invalidate */
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mcrr p15, 0, ip, r0, c5 /* either way, invalidate instruction cache */
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bx lr
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/*
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* Flushes the TLB for this page in the current address-space context.
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*
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* Parameters:
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* - vmaPage = The page to be invalidated.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForPage
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/*
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* Flushes the TLB for this page in a specified address-space context.
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*
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* Parameters:
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* - vmaPage = The page to be invalidated.
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* - uiASID = Address-space identifier.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForPageAndContext
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_MmFlushTLBForPage:
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mrc p15, 0, r1, c13, c0, 1 /* get current context */
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_MmFlushTLBForPageAndContext:
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and r1, r1, #0xFF /* get ASID */
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mov ip, # SYS_PAGE_SIZE
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sub ip, ip, #1
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bic r0, r0, ip /* mask off "page" bits */
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orr r0, r0, r1 /* add in specified ASID */
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mcr p15, 0, r0, c8, c5, 1 /* invalidate TLB by virtual address */
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bx lr
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/*
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* Flushes the TLB for this section in the current address-space context.
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*
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* Parameters:
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* - vmaPage = The section to be invalidated.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForSection
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/*
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* Flushes the TLB for this section in a specified address-space context.
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*
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* Parameters:
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* - vmaSection = The page to be invalidated.
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* - uiASID = Address-space identifier.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForSectionAndContext
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_MmFlushTLBForSection:
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mrc p15, 0, r1, c13, c0, 1 /* get current context */
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_MmFlushTLBForSectionAndContext:
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and r1, r1, #0xFF /* get ASID */
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mov ip, # SYS_SEC_SIZE
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sub ip, ip, #1
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and r0, r0, ip /* r0 = first page to invalidate */
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orr r0, r0, r1
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add ip, r0, # SYS_SEC_SIZE /* ip = last page to invalidate */
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.flush1:
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mcr p15, 0, r0, c8, c5, 1 /* invalidate TLB by virtual address */
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add r0, r0, # SYS_PAGE_SIZE /* next page */
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cmp r0, ip /* are we done? */
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bxeq lr /* yes, bug out */
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b .flush1 /* no, keep going */
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/*
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* Returns the value of TTB0, the pointer to the process-level TTB.
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*
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* Parameters:
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* None.
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*
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* Returns:
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* A pointer to the process-level TTB.
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*/
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.globl _MmGetTTB0
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_MmGetTTB0:
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mrc p15, 0, r0, c2, c0, 0
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bx lr
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/*
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* Sets the value of TTB0, the pointer to the process-level TTB.
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*
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* Parameters:
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* - pTTB = Pointer to the new process-level TTB.
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*
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* Returns:
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* Nothing.
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*
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* N.B.:
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* Only call this from within kernel code, as otherwise the results can be unpredictable.
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*/
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.globl _MmSetTTB0
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_MmSetTTB0:
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 /* clear caches */
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mcr p15, 0, ip, c8, c7, 0 /* clear TLB */
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instr_barrier
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mcr p15, 0, r0, c2, c0, 0 /* set TTB0 */
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mrc p15, 0, ip, c0, c0, 0 /* read ID register */
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instr_barrier
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bx lr
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@ -32,7 +32,7 @@ MAKEFLAGS += -rR
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CRBASEDIR := $(abspath ../..)
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include $(CRBASEDIR)/armcompile.mk
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MM_OBJS = memmgr.o vmmap.o pagealloc.o kernel_space.o
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MM_OBJS = lowlevel.o memmgr.o vmmap.o pagealloc.o kernel_space.o
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MM_INIT_OBJS = init_heap.o
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all: kernel-mm.o
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190
kernel/mm/lowlevel.S
Normal file
190
kernel/mm/lowlevel.S
Normal file
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@ -0,0 +1,190 @@
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/*
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* This file is part of the COMROGUE Operating System for Raspberry Pi
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*
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* Copyright (c) 2013, Eric J. Bowersox / Erbosoft Enterprises
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* All rights reserved.
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*
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* This program is free for commercial and non-commercial use as long as the following conditions are
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* adhered to.
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*
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* Copyright in this file remains Eric J. Bowersox and/or Erbosoft, and as such any copyright notices
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* in the code are not to be removed.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this list of conditions and
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* the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* "Raspberry Pi" is a trademark of the Raspberry Pi Foundation.
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*/
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#include <comrogue/internals/asm-macros.h>
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#include <comrogue/internals/mmu.h>
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.section ".text"
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/*---------------------------------------
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* Low-level memory-management functions
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*---------------------------------------
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*/
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/*
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* Flushes the system cache of all data on a page. Optionally writes back writeable data before flushing.
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*
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* Parameters:
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* - vmaPage = The page to be invalidated.
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* - bWriteback = TRUE to write back before invalidating, FALSE to not do so.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushCacheForPage
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_MmFlushCacheForPage:
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mov r2, # SYS_PAGE_SIZE
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sub r2, r2, #1
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orr ip, r0, r2 /* expand so that [r0, ip] is the range to invalidate */
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bic r0, r0, r2
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tst r1, r1 /* is this a writeable page? */
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mcrrne p15, 0, ip, r0, c14 /* yes, clean and invalidate */
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mcrreq p15, 0, ip, r0, c6 /* no, just invalidate */
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mcrr p15, 0, ip, r0, c5 /* either way, invalidate instruction cache */
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bx lr
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/*
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* Flushes the system cache of all data in a section. Optionally writes back writeable data before flushing.
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*
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* Parameters:
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* - vmaSection = The section to be invalidated.
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* - bWriteback = TRUE to write back before invalidating, FALSE to not do so.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushCacheForSection
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_MmFlushCacheForSection:
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mov r2, # SYS_SEC_SIZE
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sub r2, r2, #1
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bic r0, r0, r2 /* expand so that [r0, ip] is the range to invalidate */
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orr ip, r0, r2
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tst r1, r1 /* is this a writeable section? */
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mcrrne p15, 0, ip, r0, c14 /* yes, clean and invalidate */
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mcrreq p15, 0, ip, r0, c6 /* no, just invalidate */
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mcrr p15, 0, ip, r0, c5 /* either way, invalidate instruction cache */
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bx lr
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/*
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* Flushes the TLB for this page in the current address-space context.
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*
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* Parameters:
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* - vmaPage = The page to be invalidated.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForPage
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/*
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* Flushes the TLB for this page in a specified address-space context.
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*
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* Parameters:
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* - vmaPage = The page to be invalidated.
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* - uiASID = Address-space identifier.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForPageAndContext
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_MmFlushTLBForPage:
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mrc p15, 0, r1, c13, c0, 1 /* get current context */
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_MmFlushTLBForPageAndContext:
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and r1, r1, #0xFF /* get ASID */
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mov ip, # SYS_PAGE_SIZE
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sub ip, ip, #1
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bic r0, r0, ip /* mask off "page" bits */
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orr r0, r0, r1 /* add in specified ASID */
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mcr p15, 0, r0, c8, c5, 1 /* invalidate TLB by virtual address */
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bx lr
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/*
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* Flushes the TLB for this section in the current address-space context.
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*
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* Parameters:
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* - vmaPage = The section to be invalidated.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForSection
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/*
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* Flushes the TLB for this section in a specified address-space context.
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*
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* Parameters:
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* - vmaSection = The page to be invalidated.
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* - uiASID = Address-space identifier.
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*
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* Returns:
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* Nothing.
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*/
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.globl _MmFlushTLBForSectionAndContext
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_MmFlushTLBForSection:
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mrc p15, 0, r1, c13, c0, 1 /* get current context */
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_MmFlushTLBForSectionAndContext:
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and r1, r1, #0xFF /* get ASID */
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mov ip, # SYS_SEC_SIZE
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sub ip, ip, #1
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and r0, r0, ip /* r0 = first page to invalidate */
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orr r0, r0, r1
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add ip, r0, # SYS_SEC_SIZE /* ip = last page to invalidate */
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.flush1:
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mcr p15, 0, r0, c8, c5, 1 /* invalidate TLB by virtual address */
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add r0, r0, # SYS_PAGE_SIZE /* next page */
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cmp r0, ip /* are we done? */
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bxeq lr /* yes, bug out */
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b .flush1 /* no, keep going */
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/*
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* Returns the value of TTB0, the pointer to the process-level TTB.
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*
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* Parameters:
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* None.
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*
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* Returns:
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* A pointer to the process-level TTB.
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*/
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.globl _MmGetTTB0
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_MmGetTTB0:
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mrc p15, 0, r0, c2, c0, 0
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bx lr
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/*
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* Sets the value of TTB0, the pointer to the process-level TTB.
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*
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* Parameters:
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* - pTTB = Pointer to the new process-level TTB.
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*
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* Returns:
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* Nothing.
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*
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* N.B.:
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* Only call this from within kernel code, as otherwise the results can be unpredictable.
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*/
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.globl _MmSetTTB0
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_MmSetTTB0:
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 /* clear caches */
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mcr p15, 0, ip, c8, c7, 0 /* clear TLB */
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instr_barrier
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mcr p15, 0, r0, c2, c0, 0 /* set TTB0 */
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mrc p15, 0, ip, c0, c0, 0 /* read ID register */
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instr_barrier
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bx lr
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