69 lines
4.2 KiB
C
69 lines
4.2 KiB
C
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/*
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* This file is part of the COMROGUE Operating System for Raspberry Pi
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*
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* Copyright (c) 2013, Eric J. Bowersox / Erbosoft Enterprises
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* All rights reserved.
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*
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* This program is free for commercial and non-commercial use as long as the following conditions are
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* adhered to.
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*
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* Copyright in this file remains Eric J. Bowersox and/or Erbosoft, and as such any copyright notices
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* in the code are not to be removed.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this list of conditions and
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* the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* "Raspberry Pi" is a trademark of the Raspberry Pi Foundation.
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*/
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#ifndef __SCTLR_H_INCLUDED
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#define __SCTLR_H_INCLUDED
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#ifdef __COMROGUE_INTERNALS__
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/*------------------------------------------------------
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* Bits in the System Control Register (SCTLR), CP15 c1
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*------------------------------------------------------
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*/
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#define SCTLR_M 0x00000001 /* MMU: 1 = enabled, 0 = disabled */
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#define SCTLR_A 0x00000002 /* Alignment check: 1 = enabled, 0 = disabled */
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#define SCTLR_C 0x00000004 /* Cache: 1 = enabled, 0 = disabled */
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#define SCTLR_CP15BEN 0x00000020 /* CP15 barrier operations: 1 = enabled (default), 0 = disabled */
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#define SCTLR_B 0x00000080 /* Endianness: 0 = default, do not modify */
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#define SCTLR_SW 0x00000400 /* SWP/SWPB instructions: 0 = disable, 1 = enable */
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#define SCTLR_Z 0x00000800 /* Branch prediction: 0 = disable, 1 = enable */
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#define SCTLR_I 0x00001000 /* Instruction cache: 0 = disable, 1 = enable */
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#define SCTLR_V 0x00002000 /* Exception vectors: 0 = 0x00000000 (configurable), 1 = 0xFFFF0000 (fixed) */
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#define SCTLR_RR 0x00004000 /* Cache strategy: 0 = normal, 1 = round-robin */
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#define SCTLR_L4 0x00008000 /* PC load reset T-bit: 0 = yes, 1 = no */
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#define SCTLR_HA 0x00020000 /* Hardware access flag: 0 = disabled, 1 = enabled */
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#define SCTLR_WXN 0x00080000 /* Write permission implies XN: 0 = no, 1 = yes */
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#define SCTLR_UWXN 0x00100000 /* Unprivileged write permission implies PL1 XN: 0 = no, 1 = yes */
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#define SCTLR_FI 0x00200000 /* Fast interrupts: 0 = normal, 1 = low-latency */
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#define SCTLR_U 0x00400000 /* unaligned access: 0 = disabled (default), 1 = enabled */
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#define SCTLR_XP 0x00800000 /* subpage AP bits: 0 = enabled, 1 = disabled */
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#define SCTLR_VE 0x01000000 /* Interrupt vectors: 0 = standard, 1 = determined by VIC */
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#define SCTLR_EE 0x02000000 /* Exception endianness: 0 = little-endian (default), 1 = big-endian */
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#define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ: 0 = disabled, 1 = enabled */
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#define SCTLR_TRE 0x10000000 /* TEX attributes remap: 0 = disabled, 1 = enabled */
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#define SCTLR_AFE 0x20000000 /* AP[0] = Access Flag: 0 = disabled, 1 = enabled */
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#define SCTLR_TE 0x40000000 /* Instruction set state for exceptions: 0 = ARM (default), 1 = Thumb */
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#endif /* __COMROGUE_INTERNALS__ */
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#endif /* __SCTLR_H_INCLUDED */
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