82 lines
4.4 KiB
C
82 lines
4.4 KiB
C
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/*
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* This file is part of the COMROGUE Operating System for Raspberry Pi
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*
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* Copyright (c) 2013, Eric J. Bowersox / Erbosoft Enterprises
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* All rights reserved.
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*
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* This program is free for commercial and non-commercial use as long as the following conditions are
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* adhered to.
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*
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* Copyright in this file remains Eric J. Bowersox and/or Erbosoft, and as such any copyright notices
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* in the code are not to be removed.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this list of conditions and
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* the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* "Raspberry Pi" is a trademark of the Raspberry Pi Foundation.
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*/
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#ifndef __AUXDEV_H_INCLUDED
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#define __AUXDEV_H_INCLUDED
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#ifdef __COMROGUE_INTERNALS__
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/*-------------------------------
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* BCM2835 auxiliary peripherals
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*-------------------------------
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*/
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/* Register physical addresses */
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#define AUX_REG_IRQ 0x20215000 /* AUX interrupt status */
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#define AUX_REG_ENABLE 0x20215004 /* AUX enable */
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#define AUX_MU_REG_THR 0x20215040 /* Mini-UART Transmitter Holding Register */
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#define AUX_MU_REG_RHR 0x20215040 /* Mini-UART Receiver Holding Register */
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#define AUX_MU_REG_IER 0x20215044 /* Mini-UART Interrupt Enable Register */
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#define AUX_MU_REG_IIR 0x20215048 /* Mini-UART Interrupt Identification Register */
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#define AUX_MU_REG_FCR 0x20215048 /* Mini-UART FIFO Control Register */
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#define AUX_MU_REG_LCR 0x2021504C /* Mini-UART Line Control Register */
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#define AUX_MU_REG_MCR 0x20215050 /* Mini-UART Modem Control Register */
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#define AUX_MU_REG_LSR 0x20215054 /* Mini-UART Line Status Register */
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#define AUX_MU_REG_MSR 0x20215058 /* Mini-UART Modem Status Register */
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#define AUX_MU_REG_SCR 0x2021505C /* Mini-UART Scratch Register */
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#define AUX_MU_REG_CNTL 0x20215060 /* Mini-UART Auxiliary Control Register */
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#define AUX_MU_REG_STAT 0x20215064 /* Mini-UART Auxiliary Status Register */
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#define AUX_MU_REG_BAUD 0x20215068 /* Mini-UART Baud Rate Register */
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#define AUX_SPI0_REG_CTL0 0x20215080 /* SPI 0 Control Register 0 */
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#define AUX_SPI0_REG_CTL1 0x20215084 /* SPI 0 Control Register 1 */
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#define AUX_SPI0_REG_STAT 0x20215088 /* SPI 0 Status Register */
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#define AUX_SPI0_REG_IO 0x20215090 /* SPI 0 Data Register */
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#define AUX_SPI0_REG_PEEK 0x20215094 /* SPI 0 Peek Register */
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#define AUX_SPI1_REG_CTL0 0x202150C0 /* SPI 1 Control Register 0 */
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#define AUX_SPI1_REG_CTL1 0x202150C4 /* SPI 1 Control Register 1 */
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#define AUX_SPI1_REG_STAT 0x202150C8 /* SPI 1 Status Register */
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#define AUX_SPI1_REG_IO 0x202150D0 /* SPI 1 Data Register */
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#define AUX_SPI1_REG_PEEK 0x202150D4 /* SPI 1 Peek Register */
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/* AUX IRQ register bits */
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#define AUX_IRQ_MU 0x00000001 /* Mini-UART has interrupt pending */
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#define AUX_IRQ_SPI0 0x00000002 /* SPI 0 has interrupt pending */
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#define AUX_IRQ_SPI1 0x00000004 /* SPI 1 has interrupt pending */
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/* AUX Enable register bits */
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#define AUX_ENABLE_MU 0x00000001 /* Mini-UART enable */
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#define AUX_ENABLE_SPI0 0x00000002 /* SPI 0 enable */
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#define AUX_ENABLE_SPI1 0x00000004 /* SPI 1 enable */
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#endif /* __COMROGUE_INTERNALS__ */
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#endif /* __AUXDEV_H_INCLUDED__ */
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